More information on the new node:
> TSMC's A14 is brand-new process technology that is based on the company's 2nd Generation GAAFET nanosheet transistors and new standard cell architecture to enable performance, power, and scaling advantages. TSMC expects its A14 to deliver a 10% to 15% performance improvement at the same power and complexity, a 25% to 30% lower power consumption at the same frequency as well as transistor count, and 20% - 23% higher transistor density (for mixed chip design and logic, respectively), compared to N2. Since A14 is an all-new node, it will require new IPs, optimizations, and EDA software than N2P (which leverages N2 IP) as well as A16, which is N2P with backside power delivery.
https://www.tomshardware.com/tech-industry/tsmc-unveils-1-4n...
To be clear, it's either 10-15% performance improvement on the same power as N2 or 25-30% lower power at the same performance as N2. It's not both.deliver a 10% to 15% performance improvement at the same power and complexity, a 25% to 30% lower power consumption at the same frequency as
What about SRAM?
At this point, the transistors will scale smaller and the eventually the whole chip will just be sram by area.
We'll just have less SRAM per core. Maybe move to eDRAM for last-level caches where speed is not so important.